View DA28F016SV-080_1356108.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

e 7/11/97 11:03 am 29052807.doc jul y 1997 order number: 290528-007 n smartvoltage technology ? user-selectable 3.3v or 5v v cc ? user-selectable 5v or 12v v pp n 65 ns access time n 1 million erase cycles per block n 30.8 mb/sec burst write transfer rate n 0.48 mb/sec sustainable write transfer rate n configurable x8 or x16 operation n 56-lead tsop and ssop type i packages n backwards-compatible with 28f016sa, 28f008sa command set n revolutionary architecture ? multiple command execution ? program during erase ? command super-set of the intel 28f008sa ? page buffer program n 2 a typical deep power-down n 32 independently lockable blocks n state-of-the-art 0.6 m etox? iv flash technology intels 28f016sv 16-mbit flashfile? memory is a revolutionary architecture which is the ideal choice for designing embedded direct-execute code and mass storage data/file flash memory systems. with innovative capabilities, low-power operation, user-selectable v pp voltage and high read/program performance, the 28f016sv enables the design of truly mobile, high-performance personal computing and communications products. the 28f016sv is the highest density, highest performance nonvolatile read/program solution for solid-state storage applications. its symmetrically-blocked architecture (100% compatible with the 28f008sa 8-mbit and 28f016sa 16-mbit flashfile memories), extended cycling, flexible v cc and v pp voltage (smartvoltage technology), fast program and read performance and selective block locking, provide a highly-flexible memory component suitable for resident flash arrays, high-density memory cards and pcmcia-ata flash drives. the 28f016svs dual read voltage enables the design of memory cards which can be read/written in 3.3v and 5v systems interchangeably. its x8/x16 architecture allows optimization of the memory-to-processor interface. the flexible block locking option enables bundling of executable application software in a resident flash array or memory card. the 28f016sv is manufactured on intels 0.6 m etox iv process technology. 28f016sv 16-mbit (1 mbit x 16, 2 mbit x 8) flashfile? memory includes commercial and extended temperature specifications
information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantabili ty, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. the 28f016sv may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained from: intel corporation p.o. box 7641 mt. prospect, il 60056-7641 or call 1-800-879-4683 or visit intels website at http:\\www.intel.com copyright ? intel corporation, 1997 cg-041493 * third-party brands and names are the property of their respective owners.
e 28f016sv flashfile? memory 3 contents page page 1.0 introduction .............................................7 1.1 enhanced features......................................7 1.2 product overview.........................................7 2.0 device pinout.............................................9 2.1 lead descriptions ......................................11 3.0 memory maps ...........................................15 3.1 extended status registers memory map ...16 4.0 bus operations, commands and status register definitions ................17 4.1 bus operations for word-wide mode (byte# = v ih ) ..............................................17 4.2 bus operations for byte-wide mode (byte# = v il )...............................................17 4.3 28f008sacompatible mode command bus definitions .............................................18 4.4 28f016svperformance enhancement command bus definitions ............................19 4.5 compatible status register........................21 4.6 global status register ...............................22 4.7 block status register.................................23 4.8 device configuration code.........................24 5.0 electrical specifications..................25 5.1 absolute maximum ratings........................25 5.2 capacitance ...............................................26 5.3 dc characteristics (v cc = 3.3v 0.3v) .....29 5.4 dc characteristics (v cc = 5v 0.5v) 5v 0.25v) ..................................................33 5.5 timing nomenclature .................................37 5.6 ac characteristicsread only operations38 5.7 power-up and reset timings.....................43 5.8 ac characteristics for we#controlled command write operations .........................44 5.9 ac characteristics for ce#controlled command write operations ) ........................49 5.10 ac characteristics for we#controlled page buffer program operations..................54 5.11 ac characteristics for ce#controlled page buffer program operations..................56 5.12 erase and word/byte program performance.................................................58 6.0 mechanical specifications.................60 appendix a: device nomenclature and ordering information .....................................61 appendix b: ordering information .................63
28f016sv flashfile? memory e 4 revision history number description -001 original version -002 added 28f016sv-065/-070 at 5v v cc and 28f016sv-075 at 3.3v v cc . improved burst write transfer rate to 30.8 mb/sec. added 56-lead ssop type i packaging information. changed v pplk from 2v to 1.5v. increased i ccr at 5v v cc and 3.3v v cc : i ccr1 from 30 ma (typ)/35 ma (max) to 40 ma (typ)/50 ma (max) @ v cc = 3.3v i ccr2 from 15 ma (typ)/20 ma (max) to 20 ma (typ)/30 ma (max) @ v cc = 3.3v i ccr1 from 50 ma (typ)/60 ma (max) to 75 ma (typ)/95 ma (max) @ v cc = 5v i ccr2 from 30 ma (typ)/35 ma (max) to 45 ma (typ)/55 ma (max) @ v cc = 5v moved ac characteristics for extended register reads into separate table. increased v pp max from 13v to 14v. added erase suspend command latency times to section 5.12 modified device nomenclature section to include ssop package option and ordering information -003 changed definition of nc. removed no internal connection to die from description. added xx to upper byte of command (data) definition in sections 4.3 and 4.4. added note to sleep command (section 4.4) denoting that the chip must be de-selected in order for the power consumption in sleep mode to reach deep power-down levels. modified parameters v and i of section 5.1 to apply to nc pins. increased i ppr (v pp read current) for v pp > v cc to 200 a at v cc = 3.3v and v cc = 5v changed v cc = 5v dc characteristics (section 5.5) marked with note 1 to indicate that these currents are specified for a cmos rise/fall time (10% to 90%) of <5 ns and a ttl rise/fall time of <10 ns. corrected the graphical representation of t whgl and t ehgl in figures 15 and 16. increased typical page buffer byte/word program times from 6.0 s to 8.0 s (byte) and 12.1 s to 16.0 s (word) @ v cc = 3.3v/ 5v and v pp = 5v : increased typ. byte/word program times (t whrh1a /t whrh1b ) for v pp = 5v (section 5.12) t whrh1a from 16.5 s to 29.0 s and t whrh1b from 24.0 s to 35.0 s at v cc =3.3v t whrh1a from 11.0 s to 20.0 s and t whrh1b from 16.0 s to 25.0 s at v cc = 5v increased typical block program times (t whrh2 /t whrh3 )for v pp = 5v (section 5.12): t whrh2 from 1.1 sec to 1.9 sec and t whrh3 from 0.8 sec to 1.2 sec at v cc = 3.3v t whrh2 from 0.8 sec to 1.4 sec and t whrh3 from 0.6 sec to 0.85 sec at v cc = 5v changed time from erase suspend command to wsm ready spec name to erase suspend latency time to read; modified typical values and added min/max values at v cc =3.3/ 5v and v pp =5v/12v (section 5.12) added erase suspend latency time to program specifications to section 5.12 minor cosmetic changes throughout document
e 28f016sv flashfile? memory 5 revision history (continued) number description -004 added 3/5# pin to block diagram (figure 1), pinout configurations (figures 2 and 3), product overview (section 1.1) and lead descriptions (section 2.1) added 3/5# pin to test conditions of i ccs specifications added 3/5# pin (y) to timing nomenclature (section 5.5) increased t phqv specifications at 5v v cc to 400 ns for e28f016sv 065 devices and 480 ns for e28f106sv 070 devices. modified power-up and reset timings (section 5.9) to include 3/5# pin: removed t 5vph and t 3vph specifications; added t plyl , t plyh , t ylph , and t yhph specifications added t phel3 and t phel5 specifications to power-up and reset timings (section 5.9) corrected tsop mechanical specification a 1 from 0.50 mm to 0.050 mm (section 6.0) corrected ssop mechanical spec. b (max) from 0.20 mm to 0.40 mm (section 6.0) minor cosmetic changes throughout document. -005 updated dc specifications: i ccd , i ppes updated ac specifications: page buffer reads: (t avav , t avqv , t elqv , and t flqv /t fhqv ) page buffer we#-controlled command writes (t elwl ) ce#-controlled command write parameters (t avav , t eleh , t ehel ) combined commercial and extended temperature information into single datasheet. -006 updated ac specifications: page buffer reads: (t avav , t avqv , t elqv , and t flqv /t fhqv ) -007 updated disclaimer
28f016sv flashfile? memory e 6 page intentionally left blank
e 28f016sv flashfile? memory 7 1.0 introduction the documentation of the intel 28f016sv memory device includes this datasheet, a detailed users manual, and a number of application notes and design tools, all of which are referenced in appendix b. the datasheet is intended to give an overview of the chip feature-set and of the operating ac/dc specifications. the 16-mbit flash product family users manual provides complete descriptions of the user modes, system interface examples and detailed descriptions of all principles of operation. it also contains the full list of software algorithm flowcharts, and a brief section on compatibility with the intel 28f008sa. a significant 28f016sv change occurred between datasheet revisions 290528-003 and 290528-004. this change centers around the addition of a 3/5# pin to the devices pinout configuration. figures 2 and 3 show the 3/5# pin assignment for tsop and ssop type 1 packages. intel recommends that all customers obtain the latest revisions of 28f016sv documentation. 1.1 enhanced features the 28f016sv is backwards compatible with the 28f016sa and offers the following enhancements: smartvoltage technology ? selectable 5v or 12v v pp v pp level bit in block status register additional ry/by# configuration ? pulse-on-program/erase additional upload device information command feedback ? device proliferation code ? device configuration code 1.2 product overview the 28f016sv is a high-performance, 16-mbit (16,777,216-bit) block erasable, nonvolatile random access memory, organized as either 1 mword x 16 or 2 mbyte x 8. the 28f016sv includes thirty-two 64-kb (65,536 byte) blo cks or thirty-two 32-kw (32,768 word) blo cks. a chip memory map is shown in figure 4. the implementation of a new architecture, with many enhanced features, will improve the device operating characteristics and result in greater product reliability and ease-of-use. the 28f016sv incorporates smartvoltage technology, providing v cc operation at both 3.3v and 5v and program and erase capability at v pp = 12v or 5v . operating at v cc = 3.3v, the 28f016sv consumes approximately one half the power consumption at 5v v cc , while 5v v cc provides the highest read performance capability. v pp = 5v operation eliminates the need for a separate 12v converter, while v pp = 12v maximizes program/erase performance. in addition to the flexible program and erase voltages, the dedicated v pp gives complete code protection with v pp v pplk . a 3/5# input pin configures the devices internal circuitry for optimal 3.3v or 5v read/program operation. a command user interface (cui) serves as the system interface betw een the microprocessor or microcontroller and the internal memory operation. internal algorithm automation allows byte/word programs and block erase operations to be executed using a two-program command sequence to the cui in the same way as the 28f008sa 8-mbit flashfile? memory. a super-set of commands has been added to the basic 28f008sa command-set to achieve higher program performance and provide additional capabilities. these new commands and features include: page buffer programs to flash command queuing capability automatic data programs during erase software locking of memory blocks two-byte successive programs in 8-bit systems erase all unlocked blocks writing of memory data is performed in either byte or word increments typically within 6 s (12v v pp )a 33% improvement over the 28f008sa. a block erase operation erases one of the 32 blocks in typically 0.6 sec (12v v pp ), independent of the other blo cks, which is about a 65% improvement over the 28f008sa.
28f016sv flashfile? memory e 8 each block can be written and erased a minimum of 100,000 cycles. systems can achieve one million block erase cycles by providing wear- leveling algorithms and graceful block retirement. these techniques have already been employed in many flash file systems and hard disk drive designs. the 28f016sv incorporates two page buffers of 256 bytes (128 words) each to allow page data programs. this feature can improve a system program performance by up to 4.8 times over previous flash memory devices, which have no page buffers. all operations are started by a sequence of program commands to the device. three status registers (described in detail later in this datasheet) and a ry/by# output pin provide information on the progress of the requested operation. while the 28f008sa requires an operation to complete before the next operation can be requested, the 28f016sv allows queuing of the next operation while the memory executes the current operation. this eliminates system overhead when writing several bytes in a row to the array or erasing several blocks at the same time. the 28f016sv can also perform program operations to one block of memory while performing erase of another block. the 28f016sv provides selectable block locking to protect code or data such as device drivers, pcmcia card information, rom-executable o/s or application code. each block has an associated nonvolatile lock-bit which determines the lock status of the block. in addition, the 28f016sv has a master write protect pin (wp#) which prevents any modifications to memory blocks whose lock-bits are set. the 28f016sv contains three types of status registers to accomplish various functions: a compatible status register (csr) which is 100% compatible with the 28f008sa flashfile memory status register. the csr, when used alone, provides a straightforward upgrade capability to the 28f016sv from a 28f008sa- based design. a global status register (gsr) which informs the system of comm and queue status, page buffer status, and overall write state machine (wsm) status. 32 block status registers (bsrs) which provide block-specific status information such as the block lock-bit status. the gsr and bsr memory maps for byte-wide and word-wide modes are shown in figures 5 and 6. the 28f016sv incorporates an open drain ry/by# output pin. this feature allows the user to or-tie many ry/by# pins together in a multiple memory configuration such as a resident flash array. other configurations of the ry/by# pin are enabled via special cui commands and are described in detail in the 16-mbit flash product family users manual. the 28f016svs enhanced upload device information command provides access to additional information that the 28f016sa previously did not offer. this command uploads the device revision number, device proliferation code and device configuration code to the page buffer. the device proliferation code for the 28f016sv is 01h, and the device configuration code identifies the current ry/by# configuration. section 4.4 documents the exact page buffer address locations for all uploaded information. a subsequent page buffer swap and page buffer read command sequence is necessary to read the correct device information. the 28f016sv also incorporates a dual chip- enable function with two input pins, ce 0 # and ce 1 #. these pins have exactly the same functionality as the regular chip-enable pin, ce#, on the 28f008sa. for minimum chip designs, ce 1 # may be tied to ground and system logic may use ce 0 # as the chip enable input. the 28f016sv uses the logical combination of these two signals to enable or disable the entire chip. both ce 0 # and ce 1 # must be active low to enable the device. if either one becomes inactive, the chip will be disabled. this feature, along with the open drain ry/by# pin, allows the system desi gner to reduce the number of control pins used in a large array of 16-mbit devices. the byte# pin allows either x8 or x16 read/programs to the 28f016sv. byte# at logic low selects 8-bit mode with address a 0 selecting between the low byte and high byte. on the other hand, byte# at logic high enables 16-bit operation with address a 1 becoming the lowest
e 28f016sv flashfile? memory 9 order address and address a 0 is not used (dont care). a device block diagram is shown in figure 1. the 28f016sv is specified for a maximum access time of 65 ns (t acc ) at 5v operation (4.75v to 5.25v) over the commercial temperature range (0 c to +70 c). a corresponding maximum access time of 75 ns at 3.3v (3.0v to 3.6v and 0 c to +70 c) is achieved for reduced power consumption applications. the 28f016sv incorporates an automatic power saving (aps) feature, which substantially reduces the active current when the device is in static mode of operation (addresses not switching). in aps mode, the typical i cc current is 1 ma at 5v (3.0 ma at 3.3v). a deep power-down mode of operation is invoked when the rp# (called pwd# on the 28f008sa) pin transitions low. this mode brings the device power consumption to less than 2.0 a, typically, and provides additional program protection by acting as a device reset pin during power transitions. a reset time of 400 ns ( 5v v cc operation) is required from rp# switching high until outputs are again valid. in the deep power- down state, the wsm is reset (any current operation will abort) and the csr, gsr and bsr registers are cleared. a cmos standby mode of operation is enabled when either ce 0 # or ce 1 # transitions high and rp# stays high with all input control pins at cmos levels. in this mode, the device typically draws an i cc standby current of 70 a at 5v v cc . the 28f016sv will be available in 56-lead, 1.2 mm thick, 14 mm x 20 mm tsop and 56-lead, 1.8 mm thick, 16 mm x 23.7 ssop type i packages. the form factor and pinout of these two packages allow for very high board layout densities. 2.0 device pinout the 28f016sv 56-lead tsop and 56-lead ssop type i pinout configurations are shown in figures 2 and 3.
28f016sv flashfile? memory e 10 output buffer output buffer input buffer input buffer i/o logic id register csr esrs data comparator cui y decoder x decoder 64-kbyte block 0 64-kbyte block 1 64-kbyte block 30 64-kbyte block 31 wsm program/erase voltage switch address counter address queue registers input buffer y gating/sensing output multiplexer gnd dq 8-15 dq 0-7 byte# ce # ce # oe# we# wp# rp# v cc v ry/by# pp a 0-20 data queue registers page buffers 1 0 3/5# 3/5# 0528_01 figure 1. 28f016sv block diagram architectural evolution includes smartvoltage technology, page buffers, queue registers and extended registers
e 28f016sv flashfile? memory 11 2.1 lead descriptions symbol type name and function a 0 input byte-select address: selects between high and low byte when device is in x8 mode. this address is latched in x8 data programs. not used in x16 mode (i.e., the a 0 input buffer is turned off when byte# is high). a 1 Ca 15 input word-select addresses: select a word within one 64-kbyte block. a 6 C15 selects 1 of 1024 rows, and a 1 C5 selects 16 of 512 columns. these addresses are latched during data programs. a 16 Ca 20 input block-select addresses: select 1 of 32 erase blocks. these addresses are latched during data programs, erase and lock block operations. dq 0 Cdq 7 input/output low-byte data bus: inputs data and commands during cui program cycles. outputs array, buffer, identifier or status data in the appropriate read mode. floated when the chip is de-selected or the outputs are disabled. dq 8 Cdq 15 input/output high-byte data bus: inputs data during x16 data program operations. outputs array, buffer or identifier data in the appropriate read mode; not used for status register reads. floated when the chip is de- selected or the outputs are disabled. ce 0 #, ce 1 # input chip enable inputs : activate the devices control logic, input buffers, decoders and sense amplifiers. with either ce 0 # or ce 1 # high, the device is de-selected and power consumption reduces to standby levels upon completion of any current data program or erase operations. both ce 0 # and ce 1 # must be low to select the device. all timing specifications are the same for both signals. device selection occurs with the latter falling edge of ce 0 # or ce 1 #. the first rising edge of ce 0 # or ce 1 # disables the device. rp# input reset/power-down: rp# low places the device in a deep power- down state. all circuits that consume static power, even those circuits enabled in standby mode, are turned off. when returning from deep power-down, a recovery time of t phqv is required to allow these circuits to power-up. when rp# goes low, any current or pending wsm operation(s) are terminated, and the device is reset. all status registers return to ready (with all status flags cleared). exit from deep power-down places the device in read array mode. oe# input output enable: gates device data through the output buffers when low. the outputs float to tri-state off when oe# is high. note: ce x # overrides oe#, and oe# overrides we#. we# input write enable: controls access to the cui, page buffers, data queue registers and address queue latches. we# is active low, and latches both address and data (command or array) on its rising edge. page buffer addresses are latched on the falling edge of we#.
28f016sv flashfile? memory e 12 2.1 lead descriptions (continued) symbol type name and function ry/by# open drain output ready/busy: indicates status of the internal wsm. when low, it indicates that the wsm is busy performing an operation. ry/by# floating indicates that the wsm is ready for new operations (or wsm has completed all pending operations), or erase is suspended, or the device is in deep power-down mode. this output is always active (i.e., not floated to tri-state off when oe# or ce 0 #, ce 1 # are high), except if a ry/by# pin disable command is issued. wp# input write protect: erase blocks can be locked by writing a nonvolatile lock-bit for each block. when wp# is low, those locked blocks as reflected by the block-lock status bits (bsr.6), are protected from inadvertent data programs or erases. when wp# is high, all blocks can be written or erased regardless of the state of the lock-bits. the wp# input buffer is disabled when rp# transitions low (deep power-down mode). byte# input byte enable: byte# low places device in x8 mode. all data is then input or output on dq 0 C 7 , and dq 8 C 15 float. address a 0 selects between the high and low byte. byte# high places the device in x16 mode, and turns off the a 0 input buffer. address a 1 , then becomes the lowest order address. 3/5# input 3.3/5.0 volt select: 3/5# high configures internal circuits for 3.3v operation. 3/5# low configures internal circuits for 5v operation. note: reading the array with 3/5# high in a 5v system could damage the device. reference the power-up and reset timings (section 5.7) for 3/5# switching delay to valid data. v pp supply program/erase power supply (12v 0.6v, 5v 0.5v) : for erasing memory array blocks or writing words/bytes/pages into the flash array. v pp = 5v 0.5v eliminates the need for a 12v converter, while connection to 12v 0.6v maximizes program/erase performance. note: successful completion of program and erase attempts is inhibited with v pp at or below 1.5v. program and erase attempts with v pp between 1.5v and 4.5v, between 5.5v and 11.4v, and above 12.6v produce spurious results and should not be attempted. v cc supply device power supply (3.3v 0.3v, 5v 0.5v, 5.0 0.25v): to switch 3.3v to 5v (or vice versa), first ramp v cc down to gnd, and then power to the new v cc voltage. do not leave any power pins floating. gnd supply ground for all internal circuitry: do not leave any ground pins floating. nc no connect: lead may be driven or left floating.
e 28f016sv flashfile? memory 13 ce # 1 28f016sa 28f032sa 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 56 55 53 54 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 e28f016sv 56-lead tsop pinout 14 mm x 20 mm top view 3/5# ce # 2 3/5# nc a 17 a 18 a 19 a 20 v cc a 15 a 14 a 13 a 12 ce # 0 v pp rp# a 11 a 10 a 9 a 8 gnd a 7 a 6 a 5 a 4 a 3 a 2 a 1 ce # 1 a 16 wp# we# oe# ry/by# gnd gnd dq 7 dq 14 dq 6 dq 13 dq 5 dq 12 dq 4 dq 11 dq 3 dq 10 byte# nc nc dq 2 dq 9 dq 1 dq 8 dq 0 a 0 dq 15 v cc v cc wp# we# oe# ry/by# gnd gnd dq 7 dq 14 dq 6 dq 13 dq 5 dq 12 dq 4 dq 11 dq 3 dq 10 byte# nc nc dq 2 dq 9 dq 1 dq 8 dq 0 a 0 dq 15 v cc v cc wp# we# oe# ry/by# gnd gnd dq 7 dq 14 dq 6 dq 13 dq 5 dq 12 dq 4 dq 11 dq 3 dq 10 byte# nc nc dq 2 dq 9 dq 1 dq 8 dq 0 a 0 dq 15 v cc v cc 28f032sa 28f016sa nc ce # 1 a 17 a 18 a 19 a 20 v cc a 15 a 14 a 13 a 12 ce # 0 v pp rp# a 11 a 10 a 9 a 8 gnd a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 16 a 17 a 18 a 19 a 20 v cc a 15 a 14 a 13 a 12 ce # 0 v pp rp# a 11 a 10 a 9 a 8 gnd a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 16 3/5# note: 56-lead tsop mechanical diagrams and dimensions are shown at the end of this datasheet. 0528_02 figure 2. 28f016sv 56-lead tsop pinout configuration shows compatibility with 28f016sa/28f032sa
28f016sv flashfile? memory e 14 nc ry/by# we# wp# oe# gnd da28f016sv 56-lead ssop standard pinout 16 mm x 23.7 mm top view 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 a 12 ce # 0 a 13 a 14 a 15 ce # 1 a 18 a 17 a 16 v cc 28f016sa 3/5# nc we# wp# oe# gnd a 12 ce # 0 a 13 a 14 a 15 ce # 1 a 20 a 19 a 18 a 17 a 16 v cc v cc ry/by# a 20 a 19 v cc dq 13 dq 5 dq 12 dq 4 dq 13 dq 5 dq 4 dq 12 dq 6 dq 14 dq 7 dq 15 dq 6 dq 14 dq 7 dq 15 28f016sa r/p# gnd byte# nc nc gnd dq 2 dq 10 dq 3 dq 11 dq 0 a 0 dq 8 dq 1 dq 9 v cc a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 9 a 10 a 11 v pp r/p# gnd byte# nc nc gnd dq 2 dq 10 dq 3 dq 11 dq 0 a 0 dq 8 dq 1 dq 9 v cc a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 9 a 10 a 11 v pp 3/5# note: 56-lead ssop mechanical diagrams and dimensions are shown at the end of this datasheet. 0528_03 figure 3. 56-lead ssop pinout configuration
e 28f016sv flashfile? memory 15 3.0 memory maps 32-kword block fffff 31 f8000 f7fff f0000 effff e8000 e7fff e0000 dffff 30 29 28 27 d8000 d7fff d0000 cffff c8000 c7fff c0000 bffff 26 25 24 23 b8000 b7fff b0000 a8fff a8000 a7fff a0000 9ffff 22 21 20 19 98000 97fff 90000 8ffff 88000 87fff 80000 7ffff 18 17 16 15 78000 77fff 70000 6ffff 68000 67fff 60000 5ffff 14 13 12 11 58000 57fff 50000 4ffff 48000 47fff 40000 3ffff 10 9 8 7 38000 37fff 30000 2ffff 28000 27fff 20000 1ffff 6 5 4 3 18000 17fff 10000 0ffff 08000 07fff 00000 2 1 0 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 64-kbyte block 1fffff 31 1f0000 1effff 1e0000 1dffff 1d0000 1cffff 1c0000 1bffff 30 29 28 27 1b0000 1affff 1a0000 19ffff 190000 18ffff 180000 17ffff 26 25 24 23 170000 16ffff 160000 15ffff 150000 14ffff 140000 13ffff 22 21 20 19 130000 12ffff 120000 11ffff 110000 10ffff 100000 0fffff 18 17 16 15 0f0000 0effff 0e0000 0dffff 0d0000 0cffff 0c0000 0bffff 14 13 12 11 0b0000 0affff 0a0000 09ffff 090000 08ffff 080000 07ffff 10 9 8 7 070000 06ffff 060000 05ffff 050000 04ffff 040000 03ffff 6 5 4 3 030000 02ffff 020000 01ffff 010000 00ffff 000000 2 1 0 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block byte-wide (x8) mode word-wide (x16) mod e a [20-0] a [20-1] 0528_04 figure 4. 28f016sv memory maps (byte-wide and word-wide modes)
28f016sv flashfile? memory e 16 3.1 extended status registers memory map x8 mode a[20-0] . . . 1f0004h 1f0003h 1f0002h 1f0000h 1f0001h 1f0005h 1f0006h 000004h 000003h 000002h 000000h 000001h 000006h 000005h 010002h reserved gsr reserved bsr 0 reserved reserved reserved reserved gsr reserved bsr 31 reserved reserved 0528_05 figure 5. extended status register memory map (byte-wide mode) x16 mode a[20-1] . . . 00002h 00000h 00001h 00003h 08001h reserved gsr reserved bsr 0 reserved reserved reserved f8002h f8000h f8001h f8003h reserved gsr reserved bsr 31 reserved reserved 0528_06 figure 6. extended status register memory map (word-wide mode)
e 28f016sv flashfile? memory 17 4.0 bus operations, commands and status register definitions 4.1 bus operations for word-wide mode (byte# = v ih ) mode notes rp# ce 1 #ce 0 # oe# we# a 1 dq 0 C15 ry/by# read 1,2,7 v ih v il v il v il v ih xd out x output disable 1,6,7 v ih v il v il v ih v ih x high z x standby 1,6,7 v ih v il v ih v ih v ih v il v ih x x x high z x deep power-down 1,3 v il xxxxx high z v oh manufacturer id 4 v ih v il v il v il v ih v il 0089h v oh device id 4,8 v ih v il v il v il v ih v ih 66a0h v oh write 1,5,6 v ih v il v il v ih v il xd in x 4.2 bus operations for byte-wide mode (byte# = v il ) mode notes rp# ce 1 #ce 0 # oe# we# a 0 dq 0C7 ry/by# read 1,2,7 v ih v il v il v il v ih xd out x output disable 1,6,7 v ih v il v il v ih v ih x high z x standby 1,6,7 v ih v il v ih v ih v ih v il v ih x x x high z x deep power-down 1,3 v il xxxxx high z v oh manufacturer id 4 v ih v il v il v il v ih v il 89h v oh device id 4,8 v ih v il v il v il v ih v ih a0h v oh write 1,5,6 v ih v il v il v ih v il xd in x notes: 1. x can be v ih or v il for address or control pins except for ry/by#, which is either v ol or v oh . 2. ry/by# output is open drain. when the wsm is ready, erase is suspended or the device is in deep power-down mode. ry/by# will be at v oh if it is tied to v cc through a resistor. ry/by# at v oh is independent of oe# while a wsm operation is in progress. 3. rp# at gnd 0.2v ensures the lowest deep power-down current. 4. a 0 and a 1 at v il provide device manufacturer codes in x8 and x16 modes respectively. a 0 and a 1 at v ih provide device id codes in x8 and x16 modes respectively. all other addresses are set to zero. 5. commands for erase, data program, or lock-block operations can only be completed successfully when v pp = v pph1 or v pp = v pph2 . 6. while the wsm is running, ry/by# in level-mode (default) stays at v ol until all operations are complete. ry/by# goes to v oh when the wsm is not busy or in erase suspend mode. 7. ry/by# may be at v ol while the wsm is busy performing various operations (for example, a status register read during a program operation). 8. the 28f016sv shares an identical device identifier (66a0h in word-wide mode, a0h in byte-wide mode) with the 28f016sa. see application note ap-393 28f016sv compatibility with 28f016sa for software and hardware techniques to differentiate between the 28f016sv and 28f016sa.
28f016sv flashfile? memory e 18 4.3 28f008sa compatible mode command bus definitions first bus cycle second bus cycle command notes oper addr data (4) oper addr data (4) read array write x xx ffh read aa ad intelligent identifier 1 write x xx 90h read ia id read compatible status register 2 write x xx 70h read x csrd clear status register 3 write x xx 50h word/byte program write x xx 40h write pa pd alternate word/byte program write x xx 10h write pa pd block erase/confirm write x xx 20h write ba xxd0h erase suspend/resume write x xx b0h write x xxd0h address data aa = array address ad = array data ba = block address csrd = csr data ia = identifier address id = identifier data pa = program address pd = program data x = dont care notes: 1. following the intelligent identifier command, two read operations access the manufacturer and device signature codes. 2. the csr is automatically available after device enters data program, erase, or suspend operations. 3. clears csr.3, csr.4 and csr.5. also clears gsr.5 and all bsr.5, bsr.4 and bsr.2 bits. see status register definitions. 4. the upper byte of the data bus (dq 8 C15 ) during command writes is a dont care in x16 operation of the device.
e 28f016sv flashfile? memory 19 4.4 28f016sv performance enhancement command bus definitions command mode notes first bus cycle second bus cycle third bus cycle oper addr data (13) oper addr data (13) oper addr data read extended status register 1 write x xx71h read ra gsrd bsrd page buffer swap 7 write x xx72h read page buffer write x xx75h read pba pd single load to page buffer write x xx74h write pba pd sequential load to page buffer x8 4,6,10 write x xxe0h write x bcl write x bch x16 4,5,6,10 write x xxe0h write x wcl write x wch page buffer write to flash x8 3,4,9,10 write x xx0ch write a 0 bc(l,h) write pa bc(h,l) x16 4,5,10 write x xx0ch write x wcl write pa wch two-byte program x8 3 write x xxfbh write a 0 wd(l,h) write pa wd(h,l) lock block/confirm write x xx77h write ba xxd0h upload status bits/confirm 2 write x xx97h write x xxd0h upload device information/confirm 11 write x xx99h write x xxd0h erase all unlocked blocks/confirm write x xxa7h write x xxd0h ry/by# enable to level-mode 8 write x xx96h write x xx01h ry/by# pulse-on-write 8 write x xx96h write x xx02h ry/by# pulse-on-erase 8 write x xx96h write x xx03h ry/by# disable 8 write x xx96h write x xx04h ry/by# pulse-on- write/erase 8 write x xx96h write x xx05h sleep 12 write x xxf0h abort write x xx80h address data ba = block address ad = array data wc (l,h) = word count (low, high) pba = page buffer address pd = page buffer data bc (l,h) = byte count (low, high) ra = extended register address bsrd = bsr data wd (l,h) = write data (low, high) pa = program address gsrd = gsr data x = dont care
28f016sv flashfile? memory e 20 notes: 1. ra can be the gsr address or any bsr address. see figures 4 and 5 for extended status register memory maps. 2. upon device power-up, all bsr lock-bits come up locked. the upload status bits command must be written to reflect the actual lock-bit status. 3. a 0 is automatically complemented to load second byte of data. byte# must be at v il . a 0 value determines which wd/bc is supplied first: a 0 = 0 looks at the wdl/bcl, a 0 = 1 looks at the wdh/bch. 4. bch/wch must be at 00h for this product because of the 256-byte (128-word) page buffer size, and to avoid writing the page buffer contents to more than one 256-byte segment within an array block. they are simply shown for future page buffer expandability. 5. in x16 mode, only the lower byte dq 0 C7 is used for wcl and wch. the upper byte dq 8C15 is a dont care. 6. pba and pd (whose count is given in cycles 2 and 3) are supplied starting in the fourth cycle, which is not shown. 7. this command allows the user to swap between available page buffers (0 or 1). 8. these commands reconfigure ry/by# output to one of three pulse-modes or enable and disable the ry/by# function. 9. program address, pa, is the destination address in the flash array which must match the source address in the page buffer. refer to the 16-mbit flash product family users manual . 10. bcl = 00h corresponds to a byte count of 1. similarly, wcl = 00h corresponds to a word count of 1. 11. after writing the upload device information command and the confirm command, the following information is output at page buffer addresses specified below: address information 06h, 07h (byte mode) device revision number 03h (word mode) device revision number 1eh (byte mode) device configuration code 0fh (dq 0 C 7 )(word mode) device configuration code 1fh (byte mode) device proliferation code (01h) 0fh (dq 8 C 15 )(word mode) device proliferation code (01h) a page buffer swap followed by a page buffer read sequence is necessary to access this information. the contents of all other page buffer locations, after the upload device information command is written, are reserved for future implementation by intel corporation. see section 4.8 for a description of the device configuration code. this code also corresponds to data written to the 28f016sv after writing the ry/by# reconfiguration command. 12. to ensure that the 28f016svs power consumption during sleep mode reaches the deep power-down current level, the system also needs to de-select the chip by taking either or both ce 0 # or ce 1 # high. 13. the upper byte of the data bus (dq 8 C15 ) during command writes is a dont care in x16 operation of the device.
e 28f016sv flashfile? memory 21 4.5 compatible status register wsms ess es dws vpps r r r 76543210 notes: csr.7 = write state machine status 1 = ready 0 = busy ry/by# output or wsms bit must be checked to determine completion of an operation (erase, erase suspend, or data program) before the appropriate status bit (ess, es or dws) is checked for success. csr.6 = erase-suspend status 1 = erase suspended 0 = erase in progress/completed csr.5 = erase status 1 = error in block erasure 0 = successful block erase if dws and es are set to 1 during an erase attempt, an improper command sequence was entered. clear the csr and attempt the operation again. csr.4 = data-write status 1 = error in data program 0 = data program successful csr.3 = v pp status 1 = v pp error detect, operation abort 0 = v pp ok the vpps bit, unlike an a/d converter, does not provide continuous indication of v pp level. the wsm interrogates v pp ?s level only after the data program or erase command sequences have been entered, and informs the system if v pp has not been switched on. vpps is not guaranteed to report accurate feedback between v pplk (max) and v pph1 (min), between v pph1 (max) and v pph2 (min) and above v pph2 (max). csr.2?0 = reserved for future enhancements these bits are reserved for future use; mask them out when polling the csr.
28f016sv flashfile? memory e 22 4.6 global status register wsms oss dos dss qs pbas pbs pbss 76543210 notes: gsr.7 = write state machine status 1 = ready 0 = busy [1] ry/by# output or wsms bit must be checked to determine completion of an operation (block lock, suspend, any ry/by# reconfiguration, upload status bits, erase or data program) before the appropriate status bit (oss or dos) is checked for success. gsr.6 = operation suspend status 1 = operation suspended 0 = operation in progress/completed gsr.5 = device operation status 1 = operation unsuccessful 0 = operation successful or currently running gsr.4 = device sleep status 1 = device in sleep 0 = device not in sleep matrix 5/4 0 0 = operation successful or currently running 0 1 = device in sleep mode or pending sleep 1 0 = operation unsuccessful 1 1 = operation unsuccessful or aborted if operation currently running, then gsr.7 = 0. if device pending sleep, then gsr.7 = 0. operation aborted: unsuccessful due to abort command. gsr.3 = queue status 1 = queue full 0 = queue available gsr.2 = page buffer available status 1 = one or two page buffers available 0 = no page buffer available the device contains two page buffers. gsr.1 = page buffer status 1 = selected page buffer ready 0 = selected page buffer busy selected page buffer is currently busy with wsm operation gsr.0 = page buffer select status 1 = page buffer 1 selected 0 = page buffer 0 selected note: 1. when multiple operations are queued, checking bsr.7 only provides indication of completion for that particular block. gsr.7 provides indication when all queued operations are completed.
e 28f016sv flashfile? memory 23 4.7 block status register bs bls bos boas qs vpps vppl r 76543210 notes: bsr.7 = block status 1 = ready 0 = busy [1] ry/by# output or bs bit must be checked to determine completion of an operation (block lock, suspend, erase or data program) before the appropriate status bits (bos, bls) is checked for success. bsr.6 = block lock status 1 = block unlocked for program/erase 0 = block locked for program/erase bsr.5 = block operation status 1 = operation unsuccessful 0 = operation successful or currently running bsr.4 = block operation abort status 1 = operation aborted 0 = operation not aborted the boas bit will not be set until bsr.7 = 1. matrix 5/4 0 0 = operation successful or currently running 0 1 = not a valid combination 1 0 = operation unsuccessful 1 1 = operation aborted operation halted via abort command. bsr.3 = queue status 1 = queue full 0 = queue available bsr.2 = v pp status 1 = v pp error detect, operation abort 0 = v pp ok bsr.1 = v pp level 1 = v pp detected at 5v 10% 0 = v pp detected at 12v 5% bsr.1 is not guaranteed to report accurate feedback between the v pph1 and v pph2 voltage ranges. programs and erases with v pp between v pplk (max) and v pph1 (min), between v pph1 (max) and v pph2 (min), and above v pph2 (max) produce spurious results and should not be attempted. bsr.1 was a reserved bit on the 28f016sa. bsr.0 = reserved for future enhancements this bits is reserved for future use; mask it out when polling the bsrs. note: 1. when multiple operations are queued, checking bsr.7 only provides indication of completion or that particular block. gsr.7 provides indication when all queued operations are completed.
28f016sv flashfile? memory e 24 4.8 device configuration code r r r r r rb2 rb1 rb0 76543210 notes: dcc.2-dcc.0 = ry/by# configuration (rb2 Crb0) 001 = level mode (default) 010 = pulse-on-program 011 = pulse-on-erase 100 = ry/by# disabled 101 = pulse-on-program/erase undocumented combinations of rb2 Crb0 are reserved by intel corporation for future implementations and should not be used. dcc.7 Cdcc.3 = reserved for future enhancements these bits are reserved for future use; mask them out when reading the device configuration code. set these bits to 0 when writing the desired ry/by# configuration to the device.
e 28f016sv flashfile? memory 25 5.0 electrical specifications 5.1 absolute maximum ratings* temperature under bias .................... 0c to +80c storage temperature ...................C65c to +125c notice: this is a production datasheet. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design. *warning: stressing the device beyond the absolute maximum ratings may cause permanent damage. these are stress ratings only. operation beyond the operating conditions is not recommended and extended exposure beyond the "operating conditions" may affect device reliability. v cc = 3.3v 0.3v systems sym parameter notes min max units test conditions t a operating temperature, commercial 1 0 70 c ambient temperature v cc v cc with respect to gnd 2 C0.2 7.0 v v pp v pp supply voltage with respect to gnd 2,3 C0.2 14.0 v v voltage on any pin (except v cc ,v pp ) with respect to gnd 2,5 C0.5 v cc + 0.5 v i current into any non-supply pin 5 30 ma i out output short circuit current 4 100 ma v cc = 5v 0.5v, 5v 0.25v systems (6) sym parameter notes min max units test conditions t a operating temperature, commercial 1 0 70 c ambient temperature v cc v cc with respect to gnd 2 C0.2 7.0 v v pp v pp supply voltage with respect to gnd 2,3 C0.2 14.0 v v voltage on any pin (except v cc ,v pp ) with respect to gnd 2,5 C2.0 7.0 v i current into any non-supply pin 5 30 ma i out output short circuit current 4 100 ma notes: 1. operating temperature is for commercial product defined by this specification. 2. minimum dc voltage is C0.5v on input/output pins. during transitions, this level may undershoot to C2.0v for periods <20 ns. maximum dc voltage on input/output pins is v cc + 0.5v which, during transitions, may overshoot to v cc + 2.0v for periods <20 ns. 3. maximum dc voltage on v pp may overshoot to +14.0v for periods <20 ns. 4. output shorted for no more than one second. no more than one output shorted at a time. 5. this specification also applies to pins marked nc. 6. 5% v cc specifications refer to the 28f016sv-065 and 28f016sv-070 in its high speed test configuration.
28f016sv flashfile? memory e 26 5.2 capacitance for a 3.3v 0.3v system: sym parameter notes typ max units test conditions c in capacitance looking into an address/control pin 168pft a = +25 c, f = 1.0 mhz c out capacitance looking into an output pin 1 8 12 pf t a = +25 c, f = 1.0 mhz c load load capacitance driven by outputs for timing specifications 1,2 50 pf for 5v 0.5v, 5v 0.25v system: sym parameter notes typ max units test conditions c in capacitance looking into an address/control pin 168pft a = +25 c, f = 1.0 mhz c out capacitance looking into an output pin 1 8 12 pf t a = +25 c, f = 1.0 mhz c load load capacitance driven by outputs for timing specifications 1,2 100 pf for v cc = 5v 0.5v 30 pf for v cc = 5v 0.25v note: 1. sampled, not 100% tested. guaranteed by design. 2. to obtain ibis models for the 28f016sv, please contact your local intel/distribution sales office.
e 28f016sv flashfile? memory 27 test points input output 2.0 0.8 0.8 2.0 2.4 0.45 ac test inputs are driven at v oh (2.4 vttl) for a logic 1 and v ol (0.45 vttl) for a logic 0. input timing begins at v ih (2.0 vttl) and v il (0.8 vttl). output timing ends at v ih and v il . input rise and fall times (10% to 90%) <10 ns. 0528_07 figure 7. transient input/output reference waveform for v cc = 5v 10% (standard testing configuration) (1) test points input output 1.5 3.0 0.0 1.5 ac test inputs are driven at 3.0v for a logic 1 and 0.0v for a logic 0. input timing begins, and output timing ends, at 1.5v. input rise and fall times (10% to 90%) <10 ns. 0528_08 figure 8. transient input/output reference waveform for v cc = 3.3v 0.3v and v cc = 5v 5% (high speed testing configuration) (2) notes: 1. testing characteristics for 28f016sv-070 (standard testing configuration) and 28f016sv-080. 2. testing characteristics for 28f016sv-065/28f016sv-075 and 28f016sv-70 (high speed testing configuration)/ 28f016sv-120.
28f016sv flashfile? memory e 28 from output under test test point 2.5 ns of 25 transmission line total capacitance = 100 pf w 0528_09 figure 9. transient equivalent testing load circuit (28f016sv-070/-080 at v cc = 5v 10%) from output under test test point total capacitance = 50 pf 2.5 ns of 50 transmission line w 0528_10 figure 10. transient equivalent testing load circuit (28f016sv-075/-120 at v cc = 3.3v 0.3v) from output under test test point total capacitance = 30 pf 2.5 ns of 83 transmission line w 0528_11 figure 11. high speed transient equivalent testing load circuit (28f016sv-065/-070 at v cc = 5v 5%)
e 28f016sv flashfile? memory 29 5.3 dc characteristics v cc = 3.3v 10%v, t a = 0c to +70c, C40c to +70c 3/5# = pin set high for 3.3v operations temp commercial extended sym parameter notes min typ max min typ max units test conditions i li input load current 1 1 1av cc = v cc max v in = v cc or gnd i lo output leakage current 1 10 10 a v cc = v cc max v out = v cc or gnd i ccs v cc standby current 1,5 70 130 70 130 a v cc = v cc max ce 0 #, ce 1 #, rp# = v cc 0.2v byte#, wp#, 3/5# = v cc 0.2v or gnd 0.2v 1 4 1 4 ma v cc = v cc max ce 0 #, ce 1 #, rp# = v ih byte#, wp#, 3/5# = v ih or v il i ccd v cc deep power-down current 1 2 10 5 15 a rp# = gnd 0.2v byte# = v cc 0.2v or gnd 0.2v i ccr 1v cc read current 1,4,5 40 50 40 55 ma v cc = v cc max cmos: ce 0 #, ce 1 # = gnd 0.2v, byte# = gnd 0.2v or v cc 0.2v, inputs = gnd 0.2v or v cc 0.2v ttl: ce 0 #, ce 1 # = v il , byte# = v il or v ih, inputs = v il or v ih f = 8 mhz, i out = 0 ma
28f016sv flashfile? memory e 30 5.3 dc characteristics (continued) v cc = 3.3v 10%v, t a = 0c to +70c, C40c to +70c 3/5# = pin set high for 3.3v operations temp commercial extended sym parameter notes min typ max min typ max units test conditions i ccr 2v cc read current 1,4, 5,6 20 30 20 35 ma v cc = v cc max cmos: ce 0 #, ce 1 # = gnd 0.2v, byte# = gnd 0.2v or v cc 0.2v, inputs = gnd 0.2v or v cc 0.2v ttl: ce 0 #, ce 1 # = v il , byte# = v il or v ih , inputs = v il or v ih f = 4 mhz, i out = 0 ma i ccw v cc program current for word or byte 1,6 8 12 8 12 ma v pp = 12v 5% program in progress 8 17 8 17 ma v pp = 5v 10% program in progress i cce v cc block erase current 1,6 6 12 6 12 ma v pp = 12v 5% block erase in progress 9 17 9 17 ma v pp = 5v 10% block erase in progress i cces v cc erase suspend current 1,2 1 4 1 4 ma ce 0 #, ce 1 # = v ih block erase suspended i pps v pp standby/ 1 1 10 3 10 a v pp v cc i ppr read current 30 200 70 200 a v pp > v cc i ppd v pp deep power-down current 1 0.2 5 0.2 5 a rp# = gnd 0.2v
e 28f016sv flashfile? memory 31 5.3 dc characteristics (continued) v cc = 3.3v 10%v, t a = 0c to +70c, C40c to +70c 3/5# = pin set high for 3.3v operations temp commercial extended sym parameter notes min typ max min typ max units test conditions i ppw v pp program current for word or byte 1,6 10 15 10 15 ma v pp = 12v 5% program in progress 15 25 15 25 ma v pp = 5v 10% program in progress i ppe v pp erase current 1,6 4 10 4 10 ma v pp = 12v 5% block erase in progress 14 20 14 20 ma v pp = 5v 10% block erase in progress i ppes v pp erase suspend current 1 30 200 70 200 a v pp = v pph1 or v pph2 block erase suspended v il input low voltage 6 C0.3 0.8 0.8 v v ih input high voltage 6 2.0 v cc + 0.3 v cc + 0.3 v v ol output low voltage 6 0.4 0.4 v v cc = v cc min and i ol = 4 ma
28f016sv flashfile? memory e 32 5.3 dc characteristics (continued) v cc = 3.3v 0.3v, t a = 0c to +70c , C40c to +85c 3/5# = pin set high for 3.3v operations temp comm/ext sym parameter notes min typ max units test conditions v oh 1 output high voltage 6 2.4 v cc C vv cc = v cc min i oh = C2.0 ma v oh 2 6 0.2 v v cc = v cc min i oh = C100 a v ppl k v pp program/erase lock voltage 3,6 0.0 1.5 v v pph1 v pp during program/erase operations 3 4.5 5.0 5.5 v v pph2 v pp during program/erase operations 3 11.4 12.0 12.6 v v lko v cc program/erase lock voltage 2.0 v notes: 1. all currents are in rms unless otherwise noted. typical values at v cc = 3.3v, v pp = 12v or 5v, t = +25c. these currents are valid for all product versions (package and speeds). 2. i cces is specified with the device de-selected. if the device is read while in erase suspend mode, current draw is the sum of i cces and i ccr . 3. block erases, word/byte programs and lock block operations are inhibited when v pp v pplk and not guaranteed in the ranges between v pplk (max) and v pph1 (min), between v pph1 (max) and v pph2 (min) and above v pph2 (max). 4. automatic power savings (aps) reduces i ccr to 3.0 ma typical in static operation. 5. cmos inputs are either v cc 0.2v or gnd 0.2v. ttl inputs are either v il or v ih . 6. sampled, but not 100% tested. guaranteed by design.
e 28f016sv flashfile? memory 33 5.4 dc characteristics v cc = 5v 0.5v, 5v 0.25v, t a = 0c to +70c, C40c to +85c 3/5# = pin set low for 5v operations temp commercial extended sym parameter notes min typ max min typ max units test conditions i li input load current 1 1 1av cc = v cc max v in = v cc or gnd i lo output leakage current 1 10 10 a v cc = v cc max v out = v cc or gnd i ccs v cc standby current 1,5 70 130 70 130 a v cc = v cc max ce 0 #, ce 1 #, rp# = v cc 0.2v byte#, wp#, 3/5# = v cc 0.2v or gnd 0.2v 2 4 2 4 ma v cc = v cc max, ce 0 #, ce 1 #, rp# = v ih byte#, wp#, 3/5# = v ih or v il i ccd v cc deep power-down current 1 2 10 5 15 a rp# = gnd 0.2v byte# = v cc 0.2v or gnd 0.2v i ccr 1v cc read current 1,4,5 75 95 75 105 ma v cc = v cc max cmos: ce 0 #, ce 1 # = gnd 0.2v, byte# = gnd 0.2v or v cc 0.2v, inputs = gnd 0.2v or, v cc 0.2v ttl: ce 0 #, ce 1 # = v il , byte# = v il or v ih , inputs = v il or v ih f = 10 mhz, i out = 0 ma
28f016sv flashfile? memory e 34 5.4 dc characteristics (continued) v cc = 5v 0.5v, 5v 0.25v, t a = 0c to +70c, C40c to +85c 3/5# = pin set low for 5v operations temp commercial extended sym parameter notes min typ max min typ max units test conditions i ccr 2v cc read current 1,4, 5,6 45 55 45 60 ma v cc = v cc max cmos: ce 0 #, ce 1 # = gnd 0.2v, byte# = gnd 0.2v or v cc 0.2v, inputs = gnd 0.2v or v cc 0.2v ttl: ce 0 #, ce 1 # = v il , byte# = v il or v ih , inputs = v il or v ih f = 5 mhz, i out = 0 ma i ccw v cc program current for word or byte 1,6 25 35 25 35 ma v pp = 12v 5% program in progress 25 40 25 40 ma v pp = 5v 10% program in progress i cce v cc block erase current 1,6 18 25 18 25 ma v pp = 12v 5% block erase in progress 20 30 20 30 ma v pp = 5v 10% block erase in progress i cces v cc erase suspend current 1,2 2 4 2 4 ma ce 0 #, ce 1 # = v ih block erase suspended i pps v pp standby /read 1 1 10 3 10 a v pp v cc i ppr current 30 200 70 200 a v pp > v cc i ppd v pp deep power- down current 1 0.2 5 0.2 5 a rp# = gnd 0.2v
e 28f016sv flashfile? memory 35 5.4 dc characteristics (continued) v cc = 5v 0.5v, 5v 0.25v, t a = 0c to +70c, C40c to +85c 3/5# = pin set low for 5v operations temp commercial extended sym parameter notes min typ max min typ max units test conditions i ppw v pp program current for word or byte 1,6 7 12 7 12 ma v pp = 12v 5% program in progress 17 22 17 22 ma v pp = 5v 10% program in progress i ppe v pp block erase current 1,6 5 10 5 10 ma v pp = 12v 5% block erase in progress 16 20 16 20 ma v pp = 5v 10% block erase in progress i ppes v pp erase suspend current 1 30 200 30 200 a v pp = v pph1 or v pph2 block erase suspended v il input low voltage 6 C0.5 0.8 0.8 v v ih input high voltage 6 2.0 v cc + 0.5 v cc + 0.5 v
28f016sv flashfile? memory e 36 5.4 dc characteristics (continued) v cc = 5v 0.5v, 5v 0.25v, t a = 0c to +70c, C40c to +85c 3/5# = pin set low for 5v operations temp comm/extended sym parameter notes min typ max units test conditions v ol output low voltage 6 0.45 v v cc = v cc min i ol = 5.8 ma v oh 1 output high voltage 6 0.85 v cc vv cc = v cc min i oh = C2.5 ma v oh 26v cc C 0.4 v cc = v cc min i oh = C100 a v ppl k v pp program/erase lock voltage 3,6 0.0 1.5 v v pph1 v pp during program/erase operations 4.5 5.0 5.5 v v pph2 v pp during program/erase operations 11.4 12.0 12.6 v v lko v cc program/erase lock voltage 2.0 v notes: 1. all currents are in rms unless otherwise noted. typical values at v cc = 5v , v pp = 12v or 5v , t = 25c. these currents are valid for all product versions (package and speeds) and are specified for a cmos rise/fall time (10% to 90%) of <5 ns and a ttl rise/fall time of <10 ns. 2. i cces is specified with the device de-selected. if the device is read while in erase suspend mode, current draw is the sum of i cces and i ccr. 3. block erases, word/byte programs and lock block operations are inhibited when v pp v pplk and not guaranteed in the ranges between v pplk (max) and v pph1 (min), between v pph1 (max) and v pph2 (min) and above v pph2 (max). 4. automatic power saving (aps) reduces i ccr to 1 ma typical in static operation. 5. cmos inputs are either v cc 0.2v or gnd 0.2v. ttl inputs are either v il or v ih . 6. sampled, not 100% tested. guaranteed by design.
e 28f016sv flashfile? memory 37 5.5 timing nomenclature all 3.3v system timings are measured from where signals cross 1.5v. for 5v systems use the st andard jedec cross point definitions (standard testing) or from where signals cross 1.5v (high speed testing). each timing parameter consists of 5 characters. some common examples are defined below: t ce t elqv time(t) from ce# (e) going low (l) to the outputs (q) becoming valid (v) t oe t glqv time(t) from oe # (g) going low (l) to the outputs (q) becoming valid (v) t acc t avqv time(t) from address (a) valid (v) to the outputs (q) becoming valid (v) t as t avwh time(t) from address (a) valid (v) to we# (w) going high (h) t dh t whdx time(t) from we# (w) going high (h) to when the data (d) can become undefined (x) pin characters pin states a address inputs h high d data inputs l low q data outputs v valid e ce# (chip enable) x driven, but not necessarily valid f byte# (byte enable) z high impedance g oe# (output enable) w we# (write enable) p rp# (deep power-down pin) r ry/by# (ready busy) v any voltage level y 3/5# pin 5v v cc at 4.5v minimum 3v v cc at 3.0v minimum
28f016sv flashfile? memory e 38 5.6 ac characteristics read only operations (1) v cc = 3.3v 0.3v, t a = 0c to +70c, C40c to +85c temp commercial extended commercial sym parameter speed C75 C100 C120 units notes min max min max min max t avav read cycle time 75 85 (10) 100 120 ns t avqv address to output delay 75 85 (10) 100 120 ns t elqv ce# to output delay 2,8 75 85 (10) 100 120 ns t phqv rp# high to output delay 480 620 620 ns t glqv oe# to output delay 2 40 45 45 ns t elqx ce# to output in low z 3,8 0 0 0ns t ehqz ce# to output in high z 3,8 30 50 50 ns t glqx oe# to output in low z 3 0 0 0ns t ghqz oe# to output in high z 3 20 20 20 ns t oh output hold from address, ce# or oe# change, whichever occurs first 3,8 0 0 0ns t flqv t fhqv byte# to output delay 3 75 85 (10) 100 120 ns t flqz byte# low to output in high z 330 3030ns t elfl t elfh ce# low to byte# high or low 3,8 5 5 5 ns extended status register reads t avel address setup to ce# going low 3,4, 8,9 000ns t avgl address setup to oe# going low 3,4,9 0 0 0 ns
e 28f016sv flashfile? memory 39 5.6 ac characteristics read only operations (1) (continued) v cc = 5v 0.5v, 5v 0.25v, t a = 0c to +70c, C40c to +85c temp commercial comm/ext speed C65 C70 C80 sym parameter v cc 5v 5%v 5v 10% 5v 10% units load 30 pf 50 pf 50 pf notes min max min max min max t avav read cycle time 65 70 80 ns t avqv address to output delay 65 70 80 ns t elqv ce# to output delay 2,8 65 70 80 ns t phqv rp# to output delay 400 480 (6) 400 (7) 480 ns t glqv oe# to output delay 2 30 30 (6) 35 (7) 35 ns t elqx ce# to output in low z 3,8 0 0 0 ns t ehqz ce# to output in high z 3,8 25 25 30 ns t glqx oe# to output in low z 3 0 0 0 ns t ghqz oe# to output in high z 3 15 15 20 ns t oh output hold from address, ce# or oe# change, whichever occurs first 3,8 0 0 0 ns t flqv t fhqv byte# to output delay 3 65 70 80 ns t flqz byte# low to output in high z 3 252530ns t elfl t elfh ce# low to byte# high or low 3,8 5 5 5 ns extended status register reads t avel address setup to ce# going low 3,4,8,9 0 0 0 ns t avgl address setup to oe# going low 3,4,9 0 0 0 ns
28f016sv flashfile? memory e 40 notes: 1. see ac input/output reference waveforms for timing measurements, figures 7 and 8. 2. oe# may be delayed up to t elqv -t glqv after the falling edge of ce#, without impacting t elqv . 3. sampled, not 100% tested. guaranteed by design 4. this timing parameter is used to latch the correct bsr data onto the outputs. 5. device speeds are defined as: 65/70 ns at v cc = 5v equivalent to 75 ns at v cc = 3.3v 70/80 ns at v cc = 5v equivalent to 120 ns at v cc = 3.3v 6. see the high speed ac input/output reference waveforms and ac testing load circuit. 7. see the standard ac input/output reference waveforms and ac testing load circuit. 8. ce x # is defined as the latter of ce 0 # or ce 1 # going low, or the first of ce 0 # or ce 1 # going high. 9. the address setup requirement for extended status register reads must only be met referenced to the falling edge of the last control signal to become active (ce 0 #, ce 1 # or oe#). for example, if ce 0 # and ce 1 # are activated prior to oe# for an extended status register read, specification t avgl must be met. on the other hand, if either ce 0 # or ce 1 # (or both) are activated after oe#, specification t avel must be referenced. 10. page buffer reads only.
e 28f016sv flashfile? memory 41 standby outputs enabled data valid device and address selection high z high z v power-down standby addresses stable valid output v ih v il v ih v il v ih v il v ih v il v cc gnd 5.0v v ih v i l t t t t t t t t t t phqv avqv glqv elqv glqx elqx avav ehqz ghqz oh addresses (a) oe# (g) we# (w) data (d/q) rp# (p) v oh v ol t avgl t avel cc cc cex# (e) (1) v power-up 0528_12 note: ce x # is defined as the latter of ce 0 # or ce 1 # going low, or the first of ce 0 # or ce 1 # going high. figure 12. read timing waveforms
28f016sv flashfile? memory e 42 high z high z addresses stable v ih v il v ih v il v ih v il v ih v il v oh v ol t t t t t t avqv glqv elqv glqx elqx avav t ehqz t ghqz oh addresses (a) byte# (f) data (dq0-dq7) oe# (g) t avfl t elfl t flqv = t avqv data output on dq0-dq7 = t elfl high z data output data output high z data (dq8-dq15) t flqz t avel t avgl v oh v ol t cex #(e) (1) 0528_13 note: ce x # is defined as the latter of ce 0 # or ce 1 # going low, or the first of ce 0 # or ce 1 # going high. figure 13. byte# timing waveforms
e 28f016sv flashfile? memory 43 5.7 power-up and reset timings rp# 3/5# 0v 3.3v v power-up cc 5.0v v cc (p) (y) (3v,5v) 4.5v plyl t t pl5v ylph t yhph t valid 5.0v outputs valid valid address data valid 3.3v outputs avqv t (a) (q) avqv t phqv t phqv t phel3 t ce # phel5 t x 0528_14 figure 14. v cc power-up and rp# reset waveforms symbol parameter notes min max unit t plyl t plyh rp# low to 3/5# low (high) 0 s t ylph t yhph 3/5# low (high) to rp# high 1 2 s t pl5v t pl3v rp# low to v cc at 4.5v minimum (to v cc at 3.0v min or 3.6v max) 20 s t phel3 rp# high to ce# low (3.3v v cc ) 1 405 ns t phel5 rp# high to ce# low (5v v cc ) 1 330 ns t avqv address valid to data valid for v cc = 5v 10% 3 70 ns t phqv rp# high to data valid for v cc = 5v 10% 3 400 ns notes: ce 0 #, ce 1 # and oe# are switched low after power-up. 1. the t ylph and/or t yhph times must be strictly followed to guarantee all other read and program specifications for the 28f016sv. 2. the power supply may start to switch concurrently with rp# going low. 3. the address access time and rp# high to data valid time are shown for 5v v cc operation of the 28f016sv-070 (standard test configuration). refer to the ac characteristics-read only operations for 3.3v v cc and 5v v cc (high speed test configuration) values.
28f016sv flashfile? memory e 44 5.8 ac characteristics for we# controlled command write operations (1) v cc = 3.3v 0.3v, t a = 0c to +70c; C40c to +85c temp commercial extended commercial sym parameter speed C75 C100 C120 unit notes min typ max min typ max min typ max t avav write cycle time 75 100 120 ns t vpwh 1,2 v pp setup to we# going high 3 100 100 100 ns t phel rp# setup to ce# going low 3,7 480 480 480 ns t elwl ce# setup to we# going low 3,7 0,10 (12) 10 10 ns t avwh address setup to we# going high 2,6 60 70 75 ns t dvwh data setup to we# going high 2,6 60 70 75 ns t wlwh we# pulse width 60 70 75 ns t whdx data hold from we# high 2 5 10 10 ns t whax address hold from we# high 2 5 10 10 ns t wheh ce# hold from we# high 3,7 5 10 10 ns t whwl we# pulse width high 15 30 45 ns t ghwl read recovery before write 30 0 0 ns t whrl we# high to ry/by# going low 3 100 100 100 ns t rhpl rp# hold from valid status register (csr, gsr, bsr) data and ry/by# high 30 0 0 ns t phwl rp# high recovery to we# going low 3 0.480 1 1 s t whgl write recovery before read 55 75 95 ns t qvvl 1,2 v pp hold from valid status register (csr, gsr, bsr) data and ry/by# high 30 0 0 s
e 28f016sv flashfile? memory 45 5.8 ac characteristics for we# controlled command write operations (1) (continued) v cc = 3.3v 0.3v, t a = 0c to +70c; C40c to +85c temp commercial extended commercial sym parameter speed C75 C100 C120 unit notes min typ max min typ max min typ max t whqv 1 duration of program operation 3,4,5, 11 5 9 tbd 5 9 tbd 5 9 tbd s t whqv 2 duration of block erase operation 3,4 0.3 0.8 10 0.3 0.8 10 0.3 0.8 10 sec
28f016sv flashfile? memory e 46 5.8 ac characteristics for we# controlled command write operations (1) (continued) v cc = 5v 0.5v, 5v 0.25v, t a = 0c to +70c, C40c to +85c temp commercial extended speed C65 C70 C80 sym parameter v cc 5v 5% 5v 10% 5v 10% unit load 30 pf 50 pf 50 pf notes min typ max min typ max min typ max t avav write cycle time 65 70 80 ns t vpwh 1 t vpwh 2 v pp setup to we# going high 3 100 100 100 ns t phel rp# setup to ce# going low 3,7 300 480 (9) 300 (10) 480 ns t elwl ce# setup to we# going low 3,7 0 0 0 ns t avwh address setup to we# going high 2,6 40 50 (9) 40 (10) 50 ns t dvwh data setup to we# going high 2,6 40 50 (9) 40 (10) 50 ns t wlwh we# pulse width 40 40 (9) 45 (10) 50 ns t whdx data hold from we# high 20 0 0 ns t whax address hold from we# high 2 5 10 10 ns t wheh ce# hold from we# high 3,7 5 10 (9) 5 (10) 10 ns t whwl we# pulse width high 15 30 (9) 15 (10) 30 ns t ghwl read recovery before write 30 0 0 ns t whrl we# high to ry/by# going low 3 100 100 100 ns t rhpl rp# hold from valid status register (csr, gsr, bsr) data and ry/by# high 30 0 0 ns
e 28f016sv flashfile? memory 47 5.8 ac characteristics for we# controlled command write operations (1) (continued) v cc = 5v 0.5v, 5v 0.25v, t a = 0c to +70c, C40c to +85c temp commercial extended speed C65 C70 C80 sym parameter v cc 5v 5% 5v 10% 5v 10% unit load 30 pf 50 pf 50 pf notes min typ max min typ max min typ max t phwl rp# high recovery to we# going low 3 0.300 1 (9) 0.300 (10) 1 s t whgl write recovery before read 55 60 65 ns t qvvl 1 t qvv l 2 v pp hold from valid status register (csr, gsr, bsr) data and ry/by# high 30 0 0 s t whqv 1 duration of program operation 3,4,5, 11 4.5 6 tbd 4.5 6 tbd 4.5 6 tbd s t whqv 2 duration of block erase operation 3,4 0.3 0.6 10 0.3 0.6 10 0.3 0.6 10 sec notes: 1. read timings during program and erase are the same as for normal read. 2. refer to command definition tables for valid address and data values. 3. sampled, not 100% tested. guaranteed by design. 4. program/erase durations are measured to valid status register (csr) data. v pp = 12v 0.6v. 5. word/byte program operations are typically performed with 1 programming pulse. 6. address and data are latched on the rising edge of we# for all command write operations. 7. ce x # is defined as the latter of ce 0 # or ce 1 # going low, or the first of ce 0 # or ce 1 # going high. 8. device speeds are defined as: 65/70 ns at v cc = 5v equivalent to 75 ns at v cc = 3.3v 70/80 ns at v cc = 5v equivalent to 120 ns at v cc = 3.3v 9. see the high speed ac input/output reference waveforms and ac testing load circuit. 10. see the standard ac input/output reference waveforms and ac testing load circuit. 11. the tbd information will be available in a technical paper. please contact intels application hotline or your local sales office for more information. 12. page buffer programs only.
28f016sv flashfile? memory e 48 v v we# (w) oe# (g) rp# (p) v pp cex # (e) (v) deep power-down ih il v v ih il v v ih il addresses (a) t avav t whax t wheh elwl t t whdx whwl t v v ih il t wlwh t dvwh v ih il v v ih v il phwl t high z in dd in in a t t qvvl2 d in il v pph2 v pplk v t vpwh2 read extended status register data data (d/q) whqv1,2 write data-write or erase setup command write valid address & data (data-write) or erase confirm command automated data-write or erase delay v v ry/by# (r) t whrl t whgl oh ol v v ih il addresses (a) t avav avwh t t whax in a read compatible status register data d in write read extended register command a=ra note 1 note 2 note 3 note 4 d out avwh t t rhpl t ghwl note 5 pph1 v note 7 note 6 t vpwh1 t qvvl1 0528_15 notes: 1. this address string depicts data program/erase cycles with corresponding verification via esrd. 2. this address string depicts data program/erase cycles with corresponding verification via csrd. 3. this cycle is invalid when using csrd for verification during data program/erase operations. 4. ce x # is defined as the latter of ce 0 # or ce 1 # going low or the first of ce 0 # or ce 1 # going high. 5. rp# low transition is only to show t rhpl ; not valid for above read and program cycles. 6. v pp voltage during program/erase operations valid at both 12v and 5v . 7. v pp voltage equal to or below v pplk provides complete flash memory array protection. figure 15. ac waveforms for command write operations
e 28f016sv flashfile? memory 49 5.9 ac characteristics for ce# controlled command write operations (1) v cc = 3.3v 0.3v, t a = 0c +70c, C40c +85c temp commercial extended commercial sym parameter speed C80 C100 C120 unit notes min typ max min typ max min typ max t avav write cycle time 80 100 120 ns t vpeh 1,2 v pp setup to ce# going high 3,7 100 100 100 ns t phwl rp# setup to we# going low 3 480 480 480 ns t wlel we# setup to ce# going low 3,7 0 0 0 ns t aveh address setup to ce# going high 2,6,7 60 70 75 ns t dveh data setup to ce# going high 2,6,7 60 70 75 ns t eleh ce# pulse width 7 65 70 75 ns t ehdx data hold from ce# high 2,7 10 10 10 ns t ehax address hold from ce# high 2,7 10 30 10 ns t ehwh we# hold from ce# high 35 0 10 ns t ehel ce# pulse width high 7 15 100 45 ns t ghel read recovery before write 30 0 0 ns t ehrl ce# high to ry/by# going low 3,7 100 1 100 ns t rhpl rp# hold from valid status register (csr, gsr, bsr) data and ry/by# high 3 0 75 0 ns t phel rp# high recovery to ce# going low 3,7 0.480 0 1 s t ehgl write recovery before read 55 95 ns
28f016sv flashfile? memory e 50 5.9 ac characteristics for ce# controlled command write operations (1) (continued) v cc = 3.3v 0.3v, t a = 0c +70c, C40c +85c temp commercial extended commercial sym parameter speed C80 C100 C120 unit notes min typ max min typ max min typ max t qvvl 1,2 v pp hold from valid status register (csr, gsr, bsr) data and ry/by# high 30 0 s t ehqv 1 duration of program operation 3,4,5,11 5 9 tbd 5 9 tbd 5 9 tbd s t ehqv 2 duration of block erase operation 3,4 0.3 0.8 10 0.3 0.8 10 0.3 0.8 10 sec
e 28f016sv flashfile? memory 51 5.9 ac characteristics for ce# controlled command write operations (1) (continued) v cc = 5v 0.5v, 5v 0.25v, t a = 0 to +70c, C40c to +85c temp commercial extended speed C65 C70 C80 sym parameter v cc 5v 5% 5v 10% 5v 10% unit load 30 pf 50 pf 50 pf notes min typ max min typ max min typ max t avav write cycle time 65 70 80 ns t vpeh 1,2 v pp setup to ce# going high 3,7 100 100 100 ns t phwl rp# setup to we# going low 3 300 480 (9) 300 (10) 480 ns t wlel we# setup to ce# going low 3,7 0 0 0 ns t aveh address setup to ce# going high 2,6,7 40 50 (9) 45 (10) 50 ns t dveh data setup to ce# going high 2,6,7 40 50 (9) 45 (10) 50 ns t eleh ce# pulse width 7 45 45 (9) 50 (10) 50 ns t ehdx data hold from ce# high 2,7 0 0 0 ns t ehax address hold from ce# high 2,7 10 10 10 ns t ehwh we# hold from ce# high 3,7 5 10 (9) 5 (10) 10 ns t ehel ce# pulse width high 715 30 (9) 15 ( 10) 30 ns t ghel read recovery before write 30 0 0 ns t ehrl ce# high to ry/by# going low 3,7 100 100 100 ns t rhpl rp# hold from valid status register (csr, gsr, bsr) data and ry/by# high 30 0 0 ns
28f016sv flashfile? memory e 52 5.9 ac characteristics for ce# controlled command write operations (1) (continued) v cc = 5v 0.5v, 5v 0.25v, t a = 0 to +70c, C40c to +85c temp commercial extended speed C65 C70 C80 sym parameter v cc 5v 5% 5v 10% 5v 10% unit load 30 pf 50 pf 50 pf notes min typ max min typ max min typ max t phel rp# high recovery to ce# going low 3,7 0.300 1 (9) 0.300 (10) 1 s t ehgl write recovery before read 55 60 65 ns t qvvl 1,2 v pp hold from valid status register (csr, gsr, bsr) data at ry/by# high 30 0 0 s t ehqv 1 duration of program operation 3,4,5,11 4.5 6 tbd 4.5 6 tbd 4.5 6 tbd s t ehqv 2 duration of block erase operation 3,4 0.3 0.6 10 0.3 0.6 10 0.3 0.6 10 sec notes: 1. read timings during program and erase are the same as for normal read. 2. refer to command definition tables for valid address and data values. 3. sampled, not 100% tested. guaranteed by design. 4. program/erase durations are measured to valid status data. v pp = 12v 0.6v. 5. word/byte program operations are typically performed with 1 programming pulse. 6. address and data are latched on the rising edge of ce# for all command write operations. 7. ce x # is defined as the latter of ce 0 # or ce 1 # going low, or the first of ce 0 # or ce 1 # going high. 8. device speeds are defined as: 65/70 ns at v cc = 5v equivalent to 75 ns at v cc = 3.3v 70/80 ns at v cc = 5v equivalent to 120 ns at v cc = 3.3v 9. see the high speed ac input/output reference waveforms and ac testing load circuit. 10. see the standard ac input/output reference waveforms and ac testing load circuit. 11. the tbd information will be available in a technical paper. please contact intels application hotline or your local sales office for more information.
e 28f016sv flashfile? memory 53 v v we# (w) oe# (g) rp# (p) v pp cex#(e) (v) deep power-down ih il v v ih il v v ih il addresses (a) t avav t ehax t ehwh wlel t t ehdx ehel t v v ih il t eleh t dveh v ih il v v ih v il phel t high z in dd in in a t t qvvl2 d in il v pplk v pph2 v pph1 v t vpeh2 read extended status register data data (d/q) ehqv1,2 write data-write or erase setup command write valid address & data (data-write) or erase confirm command automated data-write or erase delay v v ry/by# (r) t ehrl t ehgl oh ol v v ih il addresses (a) t avav aveh t t ehax in a read compatible status register data d in write read extended register command a=ra note 1 note 2 note 3 note 4 d out aveh t t rhpl t ghel note 5 note 6 note 7 t vpeh1 t qvvl1 0528_16 notes: 1. this address string depicts data program/erase cycles with corresponding verification via esrd. 2. this address string depicts data program/erase cycles with corresponding verification via csrd. 3. this cycle is invalid when using csrd for verification during data program/erase operations. 4. ce x # is defined as the latter of ce 0 # or ce 1 # going low or the first of ce 0 # or ce 1 # going high. 5. rp# low transition is only to show t rhpl ; not valid for above read and write cycles. 6. v pp voltage during program/erase operations valid at both 12v and 5v . 7. v pp voltage equal to or below v pplk provides complete flash memory array protection. figure 16. alternate ac waveforms for command write operations
28f016sv flashfile? memory e 54 5.10 ac characteristics for we# controlled page buffer write operations (1) v cc = 3.3v 0.3v, t a = 0c to +70c, C40c to +85c temp commercial/extended sym parameter speed C75, C100, C120 unit notes min typ max t avwl address setup to we# going low 2 0 ns v cc = 5v 0.5v, 5v 0.25v, t a = 0c to +70c, C40c to +85c temp commercial comm/ext speed C65 C70 C80 sym parameter v cc 5v 5% 5v 10% 5v 10% unit load 30 pf 50 pf 50 pf notes min typ max min typ max min typ max t avwl address setup to we# going low 20 0 0 ns notes: 1. all other specifications for we# controlled write operations can be found in section 5.8. 2. address must be valid during the entire we# low pulse. 3. device speeds are defined as: 65/70 ns at v cc = 5v equivalent to 75 ns at v cc = 3.3v 70/80 ns at v cc = 5v equivalent to 120 ns at v cc = 3.3v 4. see the high speed ac input/output reference waveforms and ac testing load circuit. 5. see the standard ac input/output reference waveforms and ac testing load circuit.
e 28f016sv flashfile? memory 55 we# (w) cex# (e) note 1 v v ih il elwl t t whdx v v ih il t wlwh t dvwh v ih il v high z in d data (d/q) v v ih il addresses (a) t whax valid t avwl t wheh t whwl 0528_17 note: 1. ce x # is defined as the latter of ce 0 # or ce 1 # going low, or the first of ce 0 # or ce 1 # going high. figure 17. we# controlled page buffer write timing waveforms (loading data to the page buffer)
28f016sv flashfile? memory e 56 5.11 ac characteristics for ce# controlled page buffer write operations (1) v cc = 3.3v 0.3v, t a = 0c to +70c, C40c to +85c temp commercial/extended sym parameter speed C75, C100, C120 unit notes min typ max t avel address setup to ce# going low 2,3 0 ns v cc = 5v 0.5v, 5v 0.25v, t a = 0c to +70c, C40c to +85c temp commercial comm/ext speed C65 C70 C80 sym parameter v cc 5v 5% 5v 10% 5v 10% unit load 30 pf 50 pf 50 pf notes min typ max min typ max min typ max t avel address setup to ce# going low 2,3 0 0 0 ns notes: 1. all other specifications for ce# controlled write operations can be found in section 5.9. 2. address must be valid during the entire we# low pulse. 3. ce x # is defined as the latter of ce 0 # or ce 1 # going low, or the first of ce 0 # or ce 1 # going high. 4. device speeds are defined as: 65/70 ns at v cc = 5v equivalent to 75 ns at v cc = 3.3v 70/80 ns at v cc = 5v equivalent to 120 ns at v cc = 3.3v 5. see the high speed ac input/output reference waveforms and ac testing load circuit. 6. see the standard ac input/output reference waveforms and ac testing load circuit.
e 28f016sv flashfile? memory 57 we# (w) v v ih il wlel t t ehdx v v ih il t eleh t dveh v ih il v high z in d data (d/q) v v ih il addresses (a) t ehax valid t avel t ehwh t ehel cex# (e) note 1 0528_18 note: 1. cex# is defined as the latter of ce 0 # or ce 1 # going low, or the first of ce 0 # or ce 1 # going high. figure 18. ce# controlled page buffer write timing waveforms (loading data to the page buffer)
28f016sv flashfile? memory e 58 5.12 erase and word/byte program performance (3,5) v cc = 3.3v 0.3v, v pp = 5v 0.5v, t a = 0c to +70c symbol parameter notes min typ (1) max units test conditions page buffer byte write time 2,6,7 tbd 8.0 tbd s page buffer word write time 2,6,7 tbd 16.0 tbd s t whrh 1a byte program time 2,7 tbd 29.0 tbd s t whrh 1b word program time 2,7 tbd 35.0 tbd s t whrh 2 block program time 2,7 tbd 1.9 tbd sec byte prog. mode t whrh 3 block program time 2,7 tbd 1.2 tbd sec word prog. mode block erase time 2,7 tbd 1.4 tbd sec full chip erase time 2,7 tbd 44.8 tbd sec erase suspend latency time to read 4 1.0 12 75 s auto erase suspend latency time to program 4.0 15 80 s v cc = 3.3v 0.3v, v pp = 12v 0.6v, t a = 0c to +70c symbol parameter notes min typ (1) max units test conditions page buffer byte write time 2,6,7 tbd 2.2 tbd s page buffer word write time 2,6,7 tbd 4.4 tbd s t whrh 1 word/byte program time 2,7 5 9 tbd s t whrh 2 block program time 2,7 tbd 0.6 2.1 sec byte prog. mode t whrh 3 block program time 2,7 tbd 0.3 1.0 sec word prog. mode block erase time 2 0.3 0.8 10 sec full chip erase time 2,7 tbd 25.6 tbd sec erase suspend latency time to read 4 1.0 9 55 s auto erase suspend latency time to program 4.0 12 60 s
e 28f016sv flashfile? memory 59 5.12 erase and word/byte program performance (3,5) (continued) v cc = 5v 0.5v, 5v 0.25v, v pp = 5v 0.5v, t a = 0c to +70c symbol parameter notes min typ (1) max units test conditions page buffer byte write time 2,6,7 tbd 8.0 tbd s page buffer word write time 2,6,7 tbd 16.0 tbd s t whrh 1a byte program time 2,7 tbd 20 tbd s t whrh 1b word program time 2,7 tbd 25 tbd s t whrh 2 block program time 2,7 tbd 1.4 tbd sec byte prog. mode t whrh 3 block program time 2,7 tbd 0.85 tbd sec word prog. mode block erase time 2,7 tbd 1.0 tbd sec full chip erase time 2,7 tbd 32.0 tbd sec erase suspend latency time to read 4 1.0 9 55 s auto erase suspend latency time to program 3.0 12 60 s v cc = 5v 0.5v, 5v 0.25v, v pp = 12v 0.6v, t a = 0c to +70c symbol parameter notes min typ (1) max units test conditions page buffer byte write time 2,6,7 tbd 2.1 tbd s page buffer word write time 2,6,7 tbd 4.1 tbd s t whrh 1 word/byte program time 2,7 4.5 6 tbd s t whrh 2 block program time 2,7 tbd 0.4 2.1 sec byte prog. mode t whrh 3 block program time 2,7 tbd 0.2 1.0 sec word prog. mode block erase time 2 0.3 0.6 10 sec full chip erase time 2,7 tbd 19.2 tbd sec erase suspend latency time to read 4 1.0 7 40 s auto erase suspend latency time to program 3.0 10 45 s notes: 1. +25c, and nominal voltages. 2. excludes system-level overhead. 3. these performance numbers are valid for all speed versions. 4. specification applies to interrupt latency for single block erase. suspend latency for erase all unlocked blocks operation extends the maximum latency time to 270 s. 5. sampled, but not 100% tested. guaranteed by design. 6. assumes using the full page buffer to program to flash (256 bytes or 128 words). 7. the tbd information will be available in a technical paper. please contact intels application hotline or your local sales office for more information.
28f016sv flashfile? memory e 60 6.0 mechanical specifications 048928.eps figure 19. mechanical specifications of the 28f016sv 56-lead tsop type i package family: thin small out-line package symbol millimeters notes minimum nominal maximum a 1.20 a 1 0.050 a 2 0.965 0.995 1.025 b 0.100 0.150 0.200 c 0.115 0.125 0.135 d 1 18.20 18.40 18.60 e 13.80 14.00 14.20 e 0.50 d 19.80 20.00 20.20 l 0.500 0.600 0.700 n56 ? 0 3 5 y 0.100 z 0.150 0.250 0.350
e 28f016sv flashfile? memory 61 e 1 y c a1 b e d see detail a detail a he a r2 a2 r1 l 1 b a 0528_20 figure 20. mechanical specifications of the 28f016sv 56-lead ssop type i package family: shrink small out-line package symbol millimeters notes minimum nominal maximum a 1.80 1.90 a1 0.47 0.52 0.57 a2 1.18 1.28 1.38 b 0.25 0.30 0.40 c 0.13 0.15 0.20 d 23.40 23.70 24.00 e 13.10 13.30 13.50 e 1 0.80 he 15.70 16.00 16.30 n56 l 1 0.45 0.50 0.55 y 0.10 a 2 3 4 b345 r1 0.15 0.20 0.25 r2 0.15 0.20 0.25
28f016sv flashfile? memory e 62 appendix a device nomenclature and ordering information product line designator for all intel flash products package da = commercial temp. 56-lead ssop e = commercial temp. 56-lead tsop t = extended temp. 56-lead ssop device type v = smartvoltage e2 8 f 06 1 sv - 6 0 access speed (ns) 5 65 ns (5v, 30 pf), 70 ns (5v), 75 ns (3.3v) 70 ns (5v, 30 pf), 80 ns (5v), 120 ns (3.3v) product family s = flashfile? memory device density 016 = 16 mbit 0528_21 valid combinations option order code v cc = 3.3v 0.3v, 50 p f load, 1.5v i/o levels (1) v cc = 5v 10%, 100 pf load ttl i/o levels (1) v cc = 5v 5%, 30 p f load 1.5v i/o levels (1) 1 e28f016sv 070 e28f016sv-120 e28f016sv-080 e28f016sv-070 2 e28f016sv 065 e28f016sv-075 e28f016sv-070 e28f016sv-065 3 da28f016sv 070 da28f016sv-120 DA28F016SV-080 da28f016sv-070 4 da28f016sv 065 da28f016sv-075 da28f016sv-070 da28f016sv-065 5 dt28f016sv 080 dt28f016sv-100 dt28f016sv-080 dt28f016sv-080 note: 1. see section 5.2 for transient input/output reference waveforms and testing load circuits.
e 28f016sv flashfile? memory 63 appendix b additional information (1,2) order number document/tool 297372 16-mbit flash product family users manual 290429 28f008sa datasheet 290490 dd28f032sa 32-mbit (2 bit x 16, 4 mbit x 8) flashfile? memory datasheet) 292092 ap-357 power supply solutions for flash memory 292123 ap-374 flash memory write protection techniques 292126 ap-377 16-mbit flash product family software drivers, 28f016sa/28f016sv/28f016xs/28f016xd 292144 ap-393 28f016sv compatibility with 28f016sa 292159 ap-607 multi-site layout planning with intels flashfile? components, including rom capability 292163 ap-610 flash memory in-system code and data update techniques 292165 ab-62 compiled code optimizations for flash memories 294016 er-33 etox? flash memory technologyinsight to intels fourth generation process innovation 297508 flashbuilder utility contact intel/distribution sales office flash cycling utility contact intel/distribution sales office 28f016sv ibis model contact intel/distribution sales office 28f016sv vhdl contact intel/distribution sales office 28f016sv timing designer library files contact intel/distribution sales office 28f016sv orcad and viewlogic schematic symbols notes: 1. please call the intel literature center at (800) 548-4725 to request intel documentation. international customers should contact their local intel or distribution sales office. 2. visit intels world wide web home page at http://www.intel.com for technical documentation and tools.

▲Up To Search▲

Price & Availability of DA28F016SV-080

	To Download DA28F016SV-080 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .